TESTLABEL	STATUS	AC_Settling(LOAD)	Max_VLOAD	Min_VLOAD	min_gain_margin	min_phase_margin	
FindACSteadyState|DC Input|POP-AC	PASS	PASS:  Voltage across LOAD has settled to (7.53023n) % and is less than or equal to Max Settling Spec of (10m) %	PASS: Max. Output1 Voltage (400.171) is less than or equal to Max. Output1 Voltage Spec (420)				
FindACSteadyState|AC Input|Multi-Tone	RUN						
Bode Plot|DC Input|POP-AC	WARN		PASS: Max. Output1 Voltage (400.171) is less than or equal to Max. Output1 Voltage Spec (420)	PASS: Min. Output1 Voltage (400.063) is greater than or equal to Min. Output1 Voltage Spec (380)	WARN: Unable to determine min_gain_margin	PASS: Phase Margin (65.7001) is greater than Min. Phase Margin (35)	
Bode Plot|AC Input|Multi-Tone	WARN		PASS: Max. Output1 Voltage (405.4) is less than or equal to Max. Output1 Voltage Spec (420)	PASS: Min. Output1 Voltage (394.23) is greater than or equal to Min. Output1 Voltage Spec (380)	WARN: Unable to determine min_gain_margin	PASS: Phase Margin (65.0557) is greater than Min. Phase Margin (35)	
Bode Plot|Generate Summary Curves	SKIP						
