baseschematic: ..\..\..\..\..\..\4_multi_tone.sxsch
log_file: ..\..\..\..\dvm_advanced.log
simulator: simplis
screenshot: schematic.png
deck: input.deck
init: input.deck.init
test_argument: FindACSteadyState|DC Input|POP_AC|PWM multiplier
datetimestamp: 11/17/2016 11:23 AM
status: RUN
feature: DVM LOAD#tran
spec: Max_VLOAD=pass,Max. Output1 Voltage (400.138) is less than or equal to Max. Output1 Voltage Spec (420)
scalar: Frequency(SRC)=50
scalar: RMS(VSRC)=114.263
scalar: VLOAD %_diff_last_2_linecycles=0.00000000106787%
spec: AC_Settling(LOAD)=pass, Voltage across LOAD has settled to (10.6787p) % and is less than or equal to Max Settling Spec of (10m) %
scalar: Avg(VLOAD Last LineCycle)=400.093
scalar: Avg(VLOAD Previous LineCycle)=400.093
scalar: VLOAD %_diff_last_2_linecycles=0.00000000106787%
scalar: Avg(VLOAD At Simulation Start Time)=400.093
stats: N/A
numgraphs: 5
graphid: 1
graphname: new#tran
sg: simplis_tran1_1
path: simplis_tran1_1.sxgph
graphid: 6
graphname: default#6#tran
sg: simplis_tran1_6
path: simplis_tran1_6.sxgph
scalar: Max(VSRC)=114.263
scalar: Min(VSRC)=114.263
scalar: Min(ISRC)=1.84145
scalar: Max(ISRC)=1.84153
graphid: 12
graphname: DVM SRC#tran
sg: simplis_tran1_12
path: simplis_tran1_12.sxgph
curve16:VSRC,FF0000
curve22:ISRC,008000
png: simplis_tran1_12.png
scalar: Max(VLOAD)=400.138
scalar: Min(VLOAD)=400.068
scalar: Max(ILOAD)=500.172m
scalar: Min(ILOAD)=500.085m
graphid: 17
graphname: DVM LOAD#tran
sg: simplis_tran1_17
path: simplis_tran1_17.sxgph
curve21:VLOAD,FF0000
curve24:ILOAD,008000
png: simplis_tran1_17.png
graphid: 26
graphname: AC#tran
sg: simplis_tran1_26
path: simplis_tran1_26.sxgph
curve30:IL,FF0000
png: simplis_tran1_26.png
rstatus: PASS
